The present invention relates to integrated circuitry, and in particular to word line driver circuitry for use in integrated circuitry such as memory.
Memory, such as dynamic random access memory (DRAM) and static random access memory (SRAM), typically include many memory cells that are capable of holding a charge that is representative of a bit of data. Typically, these memory cells are arranged in a two-dimensional array of intersecting rows and columns. Data is written to and retrieved from the memory cells by selectively accessing the memory cells.
Memory cells can be accessed by applying activation voltages to word lines and bit lines. In general, word lines activate memory cells and bit lines provide data to or retrieve data from the activated memory cells. Conventionally, a word line runs adjacent to each row of memory cells and a bit line runs adjacent to each column of memory cells. It is understood this arrangement is not fixed and that memory can be constructed such that word lines run adjacent to columns of memory cells and bits lines run adjacent to rows of memory cells.
When memory access is desired, an activation voltage is applied to the word line by a word line driver so that a desired function (e.g., read or write) is performed. More particularly, when an activation voltage is applied to the word line, this activates circuitry (e.g., passgate transistor) in the memory cell that enables a bit line to write data to or retrieve data from the activated memory cell. When memory access is not needed, the word line driver may apply a deactivation voltage to cease the memory access function.
These activation and deactivation voltages may be applied by word line drivers. For example, to write data to a memory cell or to read data from a memory cell, a word line may need to be driven to a positive voltage level. During periods of inactivity (i.e., no memory access is being performed), the voltage on the word lines may be driven to a low voltage such as a ground voltage or a negative voltage.
It is desirable to drive the word line to a negative voltage level or a ground voltage level when the memory cell is not being accessed to ensure that the memory cell does not loose its charge. However, driving the word line to such voltages creates problems such as bouncing. Bouncing is an undesirable voltage spike or ripple that occurs on the voltage source providing the ground or negative voltage when the voltage on a word line is being pulled down from an activation voltage. Deleterious effects of bouncing have been known to become more pronounced the faster the word line is pulled down.
Excessive leakage current is another problem that has proved difficult for conventional word line drivers to handle. Such excessive leakage current can be caused when adjacent rows of word lines short or when a word line short circuits with an overlapping bit line. These short circuits can cause excessive leakage current that can damage the memory circuitry, result in increased power consumption, or result in faulty memory operation.
Moreover, in conventional memory arrangements, the presence of a short circuit can render a whole segment (which may be connected to a common voltage source) of memory permanently inoperable. These segments typically constitute “large” blocks of memory within the memory array, (similar in the way a hard disk cluster is a “large” portion of hard drive space within a hard drive). Depending on the word line driver circuitry being implemented in the memory, failure of one word line can propagate and render an entire segment inoperable.
Such a failure, which can be caused by a short circuit condition, can occur when a word line fault test is being performed. A word line fault test tests whether a word line is faulty (e.g., short circuited). Conventional word line driver circuitry is unable to prevent the segment from becoming permanently inoperable in the event a word line fault test is performed on a faulty word line. Thus, when testing voltages are applied to a word line to test whether that word line is faulty, a faulty word line results in rendering not just the memory cells associated with that word line inoperable, but all the memory cells in that segment are rendered inoperable.
Therefore, it is an object of the invention to provide word line driver circuitry that provides rapid pull down, while providing protection against short circuit conditions.